I am operating a transimpedance amplifier for a photodiode
deliberately well past the cutoff frequency of about 40 Hz because I
want to keep the thermal noise down. A generic picture of the
frequency response is given on Figure 2b on page 2 in:
http://www.ece.utexas.edu/~slyan/archive/ee382m_spring04/notes/lecture16.pdf
I use a second stage of amplification (essentially a differentiator)
to compensate for the gain roll-off and the circuit does quite a good
job of flattening the gain curve up to about 200 kHz. It also does a
somwhat decent job of compensating for the 90รโรยฐ phase shift introduced in the
first stage, but not out to nearly as high a frequency. I calibrate
the circuits as carefully as I can to measure and digitally subtract
the actual phase shift because it turns out that any uncalibrated
phase shift is quite detrimental. I would like to design a smaller
total phase shift directly into the analog circuit.
I know how to design a circuit to compensate for the gain roll off --
matching the break points etc., but I'm not familiar with designing an analog
circuit for optimizing the nulling of the phase shift. I've read a couple of
papers on phase compensation, such as found in:
http://amsc.tamu.edu/SIS/Publications/pub/jounal/2003_6.pdf
but I don't think that's what I'm looking for. Can you provide a
tutorial for useful methods for optimizing the compensation for the
phase shift, even at the expense of an optimal compensation for the
gain rolloff?
deliberately well past the cutoff frequency of about 40 Hz because I
want to keep the thermal noise down. A generic picture of the
frequency response is given on Figure 2b on page 2 in:
http://www.ece.utexas.edu/~slyan/archive/ee382m_spring04/notes/lecture16.pdf
I use a second stage of amplification (essentially a differentiator)
to compensate for the gain roll-off and the circuit does quite a good
job of flattening the gain curve up to about 200 kHz. It also does a
somwhat decent job of compensating for the 90รโรยฐ phase shift introduced in the
first stage, but not out to nearly as high a frequency. I calibrate
the circuits as carefully as I can to measure and digitally subtract
the actual phase shift because it turns out that any uncalibrated
phase shift is quite detrimental. I would like to design a smaller
total phase shift directly into the analog circuit.
I know how to design a circuit to compensate for the gain roll off --
matching the break points etc., but I'm not familiar with designing an analog
circuit for optimizing the nulling of the phase shift. I've read a couple of
papers on phase compensation, such as found in:
http://amsc.tamu.edu/SIS/Publications/pub/jounal/2003_6.pdf
but I don't think that's what I'm looking for. Can you provide a
tutorial for useful methods for optimizing the compensation for the
phase shift, even at the expense of an optimal compensation for the
gain rolloff?